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1 ? HIP6602B dual channel synchronous rectified buck mosfet driver the HIP6602B is a high frequency, two power channel mosfet driver specifically designed to drive four power n-channel mosfets in a synchronous rectifi ed buck converter topology. this device is available in either a 14-lead soic or a 16-lead qfn package with a pad to thermally enhance the package. these drivers combined with a hip63xx or isl65xx series of multi-phase buck pwm controllers and mosfets form a complete core voltage regulator solution for advanced microprocessors. the HIP6602B drives both upper and lower gates over a range of 5v to 12v. this drive-voltage flex ibility provides the advantage of optimizing applications involvi ng trade-offs between switching losses and conduction losses. the output drivers in the HIP6602B have the capacity to efficiently switch power mosfets at high fre quencies. each driver is capable of driving a 3000pf load with a 30ns propagation delay and 50ns transition time. this device implements bootstrapping on the upper gates with a single external capac itor and resistor required for each power channel. this reduces implem entation complexity and allows the use of higher performance, cost effective, n-channel mosfets. adaptive shoot-through protection is integrated to prevent both mosfets from conducting simultaneously . features ? drives four n-channel mosfets ? adaptive shoot-through protection ? internal bootstrap devices ? supports high switching frequency - fast output rise time - propagation delay 30ns ? small 14-lead soic package ? smaller 16-lead qfn thermally enhanced package ? 5v to 12v gate-drive volt ages for optimal efficiency ? three-state input for bridge shutdown ? supply undervoltage protection ? pb-free product now available (so8) ? qfn package: - compliant to jedec pub95 mo-220 qfn - quad flat no leads - package outline - near chip scale package footprint, which improves pcb efficiency and has a thinner profile applications ? core voltage supplies for intel pentium? iii and amd? athlon tm microprocessors. ? high-frequency, low-profile dc-dc converters ? high-current, low-voltage dc-dc converters note 1. intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb an d pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020b. pinouts ordering information part number temp. range (c) package pkg. dwg. # HIP6602Bcb 0 to 85 14 ld soic m14.15 HIP6602Bcb-t 14 ld soic tape and reel HIP6602Bcbz (see note 1) 0 to 85 14 ld soic (pb-free) m14.15 HIP6602Bcbz-t (see note 1) 14 ld soic (pb-free) tape and reel HIP6602Bcr 0 to 85 16 ld 5x5 qfn l16.5x5 HIP6602Bcr-t 16 ld 5x5 qfn tape and reel HIP6602Bcb/HIP6602Bcbz (soic) top view HIP6602Bcr (16 lead qfn) top view pwm1 pwm2 gnd lgate1 1 2 3 4 14 13 12 phase1 ugate1 boot1 pvcc 1 2 10 9 8 7 6 5 boot2 ugate2 phase2 vcc pgnd lgate2 11 1 3 4 15 gnd lg1 pvcc pgnd pwm2 pwm1 vcc phase1 16 14 13 2 12 10 9 11 6 578 ug1 boot1 boot2 ug2 nc lg2 phase2 nc data sheet caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2002-2004. all rights reserved all other trademarks mentioned are the property of their resp ective owners. fn9076.4 june 2004 n o t r e c o m m e n d e d f o r n e w d e s i g n s i n t e r s i l r e c o m m e n d s : i s l 6 6 1 2 , i s l 6 6 1 2 a , i s l 6 6 1 3 , i s l 6 6 1 3 a , i s l 6 6 1 4 , i s l 6 6 1 4 a
2 block diagram typical application - 2 cha nnel converter using a hip6302 and a HIP6602B gate driver vcc pwm1 +5v 10k 10k control logic shoot- through protection boot1 ugate1 phase1 lgate1 pgnd pwm2 10k 10k shoot- through protection boot2 ugate2 phase2 lgate2 +5v gnd pvcc pvcc pvcc pvcc pgnd pgnd HIP6602B pad package must be soldered to the pc board for HIP6602Bcr, the pad on the bottom side of the main control hip6302 fb +5v comp pwm1 pwm2 isen2 vsen fs/dis isen1 gnd boot2 ugate2 phase2 lgate2 boot1 ugate1 lgate1 pwm1 pvcc +5v/12v vcc +12v dual driver HIP6602B pgnd v cc +v core pwm2 pgood vid +12v gnd phase1 +12v HIP6602B
3 typical application - 4 cha nnel converter using a hip6303 and HIP6602B gate driver main control hip6303 fb +5v comp pwm1 pwm2 isen2 pwm3 pwm4 isen4 vsen fs/dis isen1 isen3 gnd boot2 ugate2 phase2 lgate2 boot1 ugate1 phase1 lgate1 pwm1 pvcc +5v/12v vcc dual driver HIP6602B boot4 ugate4 phase4 lgate4 boot3 ugate3 phase3 lgate3 pwm3 pvcc vcc dual driver HIP6602B v cc +v core pwm2 pwm4 en vid pgood +12v +12v +12v +12v +12v +5v/12v +12v pgnd gnd pgnd gnd HIP6602B
4 absolute m aximum ratings supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15v supply voltage (pvcc) . . . . . . . . . . . . . . . . . . . . . . . . . vcc + 0.3v boot voltage (v boot - v phase ) . . . . . . . . . . . . . . . . . . . . . . .15v input voltage (v pwm ) . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 7v ugate. . . . . . .v phase - 5v(<400ns pulse width) to v boot + 0.3v v phase -0.3v(>400ns pulse width) to v boot + 0.3v lgate . . . . . . . . . gnd - 5v(<400ns pulse width) to v pvcc + 0.3v gnd -0.3v(>400ns pulse width) to v pvcc + 0.3v phase. . . . . . . . . . . . . . . . . . gnd -5v(<400ns pulse width) to 15v gnd -0.3v(>400ns pulse width) to 15v esd rating human body model (per mil-std-883 method 3015.7) . . . . .3kv machine model (per eiaj ed-4701 method c-111) . . . . . . .200v operating conditions ambient temperature range . . . . . . . . . . . . . . . . . . . . 0c to 85c maximum operating junction temperatur e . . . . . . . . . . . . . . 125c supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12v 10% supply voltage range pvcc . . . . . . . . . . . . . . . . . . . . . 5v to 12v thermal information thermal resistance ja (c/w) jc (c/w) soic package (note 1) . . . . . . . . . . . . 68 n/a qfn package (note 2). . . . . . . . . . . . . 36 6 maximum junction temperature (plastic package) . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c (soic - lead tips only) for recommended soldering conditions see tech brief tb389. caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mounted on a high effective ther mal conductivity test board in free air. see tech brief tb379 f or details. 2. ja is measured in free air with the component mounted on a high e ffective thermal conductivity test board with ?direct attach? fe atures. jc, the ?case temp? is measured at the center of the expos ed metal pad on the package underside. see tech brief tb379. electrical specifications recommended operating conditions, unless otherwise specified. parameter symbol test conditions min typ max units vcc supply current bias supply current i vcc f pwm = 500khz, v pvcc = 12v - 3.7 5.0 ma power supply current i pvcc f pwm = 500khz, v pvcc = 12v - 2.0 4.0 ma power-on reset vcc rising threshold 9.7 9.95 10.4 v vcc falling threshold 7.3 7.6 8.0 v pwm input input current i pwm v pwm = 0 or 5v (see block diagram) - 500 - a pwm rising threshold v pvcc = 12v 3.45 3.6 - v pwm falling threshold v pvcc = 12v - 1.45 1.55 v ugate rise time tr ugate v pvcc = v vcc = 12v, 3nf load - 20 - ns lgate rise time tr lgate v pvcc = v vcc = 12v, 3nf load - 50 - ns ugate fall time tf ugate v pvcc = v vcc = 12v, 3nf load - 20 - ns lgate fall time tf lgate v pvcc = v vcc = 12v, 3nf load - 20 - ns ugate turn-off propagation delay tpdl ugate v pvcc = v vcc = 12v, 3nf load - 30 - ns lgate turn-off propagation delay tpdl lgate v pvcc = v vcc = 12v, 3nf load - 20 - ns shutdown window 1.4 - 3.6 v shutdown holdoff time - 230 - ns output upper drive source impedance r ugate v vcc = 12v, v pvcc = 5v - 1.7 3.0 ? v vcc = v pvcc = 12v - 3.0 5.0 ? upper drive sink impedance r ugate v vcc = 12v, v pvcc = 5v - 2.3 4.0 ? v vcc = v pvcc = 12v - 1.1 2.0 ? lower drive source current i lgate v vcc = 12v, v pvcc = 5v 400 580 - ma v vcc = v pvcc = 12v 500 730 - ma lower drive sink impedance r lgate v vcc = 12v, v pvcc = 5v or 12v - 1.6 4.0 ? HIP6602B
5 functional pin descriptions pwm1 (pin 1) and pwm2 (pin 2), (pins 15 and 16 qfn) the pwm signal is the control input for the driver. the pwm signal can enter three distinct states during operation, see the three-state pwm input section under description for further details. connect this pin to th e pwm output of the controller. gnd (pin 3), (pin 1 qfn) bias and reference ground. all signals are referenced to this node. lgate1 (pin 4) and lgate2 (pin 7), (pins 2 and 6 qfn) lower gate drive outputs. connect to gates of the low-side power n-channel mosfets. pvcc (pin 5), (pin 3 qfn) this pin supplies the upper and lower gate drivers bias. connect this pin from +12v down to +5v. pgnd (pin 6), (pin 4 qfn) this pin is the power ground return for the lower gate drivers. phase2 (pin 8) and phase1 (pin 13), (pins 7 and 13 qfn) connect these pins to the source of the upper mosfets and the drain of the lower mosfets. the phase voltage is monitored for adaptive shoot-through protection. these pins also provide a return path for the upper gate drive. ugate2 (pin 9) and ugate1 (pin 12), (pins 9 and 12 qfn) upper gate drive outputs. connect to gate of high-side power n-channel mosfets. boot 2 (pin 10) and boot 1 (pin 11), (pins 10 and 11 qfn) floating bootstrap supply pins for the upper gate drivers. connect a bootstrap capacitor between these pins and the corresponding phase pin. the boo tstrap capacitor provides the charge to turn on the upper mosfets. a resistor in series with boot capacitor is required in certain applications to reduce ringing on the boot pin. see the internal bootstrap device section under description for guidance in choosing the appropriate resistor and capacitor value. vcc (pin 14), (pin 14 qfn) connect this pin to a +12v bias supply. place a high quality bypass capacitor from this pin to gnd. to prevent forward biasing an internal diode, this pin should be more positive then pvcc during converter start-up description operation designed for versatility and speed, the HIP6602B two channel, dual mosfet driver controls both high-side and low-side n-channel fets from two externally provided pwm signals. the upper and lower gates are held low until the driver is initialized. once the vcc voltage surpasses the vcc rising threshold (see electrical specifications ), the pwm signal takes control of gate transitions. a rising edge on pwm initiates the turn-off of the lower mosfet (see timing diagram ). after a short propagation delay [tpdl lgate ], the lower gate begins to fall. typical fall times [tf lgate ] are provided in the electrical specifications section. adaptive shoot-through circuitry monitors the lgate voltage and determines the upper gate delay time [tpdh ugate ] based on how quickly the lgate voltage drops below 2.2v. this prevents both the lower and upper mosfets from conducting simultaneously or s hoot-through. once this delay period is complete the upper gate drive begins to rise [tr ugate ] and the upper mosfet turns on. timing diagram . pwm ugate lgate tpdl lgate tf lgate tpdh ugate tr ugate tpdl ugate tf ugate tpdh lgate tr lgate HIP6602B
6 a falling transition on pwm indicates the turn-off of the upper mosfet and the turn-on of the lower mosfet. a short propagation delay [tpdl ugate ] is encountered before the upper gate begins to fall [tf ugate ]. again, the adaptive shoot-through circuitry determines the lower gate delay time, tpdh lgate . the phase voltage is monitored and the lower gate is allowed to rise after phase drops below 0.5v. the lower gate then rises [tr lgate ], turning on the lower mosfet. three-state pwm input a unique feature of the HIP6602B drivers is the addition of a shutdown window to the pwm input. if the pwm signal enters and remains within the shutdown window for a set holdoff time, the output drivers are disabled and both mosfet gates are pulled and held low. the shutdown state is removed when the pwm signal moves outside the shutdown window. otherwise, the pwm rising and falling thresholds outlined in the electrical specifications determine when the lower and upper gates are enabled. adaptive shoot-through protection the drivers incorporate adaptive shoot-through protection to prevent upper and lower mosfets from conducting simultaneously and shorting the input supply. this is accomplished by ensuring the falling gate has turned off one mosfet before the other is allowed to rise. during turn-off of the lower mosfet, the lgate voltage is monitored until it reaches a 2.2v threshold, at which time the ugate is released to rise. adaptive shoot-through circuitry monitors the phase voltage during ugate turn-off. once phase has dropped below a threshold of 0.5v, the lgate is allowed to rise. if the ph ase does not drop below 0.5v within 250ns, lgate is allowed to rise. this is done to generate the bootstrap refresh signal. phase continues to be monitored during the lower gate rise time. if the phase voltage exceeds the 0.5v threshold during this period and remains high for longer than 2s, the lgate transitions low. this is done to make the lower mosfet emulate a diode. both upper and lower gates are then held low until the next rising edge of the pwm signal. power-on reset (por) function during initial start-up, the v cc voltage rise is monitored and gate drives are held low until a typical vcc rising threshold of 9.95v is reached. once the rising vcc threshold is exceeded, the pwm input signal takes control of the gate drives. if vcc drops below a typical vcc falling threshold of 7.6v during operation, then bo th gate drives are again held low. this condition persists until the vcc voltage exceeds the vcc rising threshold. internal bootstrap device the HIP6602B features an inter nal bootstrap device. simply adding an external capacitor across the boot and phase pins completes the bootstrap circuit. the bootstrap capacitor must have a maximum voltage rating above pvcc + 5v. the bootstrap capacitor can be chosen from the following equation: where q gate is the amount of gate charge required to fully charge the gate of the upper mosfet. the ? v boot term is defined as the allowable droop in the rail of the upper drive. as an example, suppose a huf76139 is chosen as the upper mosfet. the gate charge, q gate , from the data sheet is 65nc for a 10v upper gate drive. we will assume a 200mv droop in drive voltage over the pwm cycle. we find that a bootstrap capacitance of at least 0.325f is required. the next larger standard value capacitance is 0.33f. in applications which require down conversion from +12v or higher and pvcc is connected to a +12v source, a boot resistor in series with the boot capacitor is required. the increased power density of these designs tend to lead to increased ringing on the bo ot and phase n odes, due to faster switching of larger currents across given circuit parasitic elements. the addition of the boot resistor allows for tuning of the circuit until the peak ringing on boot is below 29v from boot to gnd and 17v from boot to vcc. a boot resistor value of 5 ? typically meets this criteria. in some applications, a well tuned boot resistor reduces the ringing on the boot pin, but the phase to gnd peak ringing exceeds 17v. a gate resistor placed in the ugate trace between the controller and upper mosfet gate is recommended to reduce the ri nging on the phase node by slowing down the upper mosfet turn-on. a gate resistor value between 2 ? to 10 ? typically reduces the phase to gnd peak ringing below 17v. gate drive voltage versatility the HIP6602B provides the user flexibility in choosing the gate drive voltage. simply applying a voltage from 5v up to 12v on pvcc will set both driver rail voltages. power dissipation package power dissipation is mainly a function of the switching frequency and total gate charge of the selected mosfets. calculating the power dissipation in the driver for a desired application is critical to ensuri ng safe operation. exceeding the maximum allowable power dissipation level will push the ic beyond the maximum recommended operating junction temperature of 125c. the maximum allowable ic power dissipation for the 14 lead soic package is approximately 1000mw. improvements in thermal transfer may be gained by increasing the pc board copper area around the HIP6602B. adding a ground pad under the ic to help transfer heat to the outer peripheral of the board will help. also keeping the leads to the ic as wide as possible and widening this these leads as soon as possible to further enhance heat transfer will also help. c boot q gate ? v boot ----------------------- - HIP6602B
7 when designing the driver into an application, it is recommended that the following calculation be performed to ensure safe operation at the desired frequency for the selected mosfets. the total chip power dissipation is approximated as: where f sw is the switching frequency of the pwm signal. q u and q l is the upper and lower gate charge determined by mosfet selection and any external capacitance added to the gate pins. the i ddq vcc product is the quiescent power of the driver and is typically 40mw. the 1.05 term is a correction factor derived from the following characterization. the base circuit for characterizing the drivers for different loadi ng profiles and frequencies is provided. c u and c l are the upper and lower gate load capacitors. decoupling capacitor s [0.15f] are added to the pvcc and vcc pins. the bootstrap capacitor value in the test circuit is 0.01f. the power dissipation approximation is a result of power transferred to and from the upper and lower gates. but, the internal bootstrap device also dissipates power on-chip during the refresh cycle. expressi ng this power in terms of the upper mosfet total gate charge is explained below. the bootstrap device conducts when the lower mosfet or its body diode conducts and pulls the phase node toward gnd. while the bootstrap device conducts, a current path is formed that refreshes the bootstrap capacitor. since the upper gate is driving a mosfet, the charge removed from the bootstrap capacitor is equivalent to the total gate charge of the mosfet. therefore, th e refresh power required by the bootstrap capacitor is equi valent to the power used to charge the gate capacitance of the upper mosfets. where q loss is the total charge remo ved from the bootstrap capacitors and provided to the upper gate loads. in figure 2, c u and c l values are the same and frequency is varied from 10khz to 1.5mhz. pvcc and vcc are tied together to a +12v supply. figure 3 shows the dissipation in the driver with 1nf loading on both gates and each individually. figure 4 is the same as figure 3 except the capacitance is increased to 3nf. the impact of loading on power dissipation is shown in figure 5. frequency is held constant while the gate capacitors are varied from 1nf to 5nf. vcc and pvcc are tied together and to a +12v supply. figures 6, 7 and 8 show the same characterization for pvcc tied to +5v instead of +12v. the gate supply voltage , pvcc, within the HIP6602B sets both upper and lower gate driver supplies at the same 5v level for the last three curves. test circuit p = 1.05 x f sw x v pvcc [ (q u1 + q u2 ) + (q l1 + q l2 ) ] + i ddq x vcc 3 2 _ p refresh f sw q loss v pvcc f sw q u v pvcc == boot1 ugate1 phase1 lgate1 pwm1 pvcc vcc 0.15f 0.15f 100k ? 2n7002 2n7002 0.01f c l c u +5v or +12v +12v HIP6602B ugate2 phase2 lgate2 100k ? 2n7002 2n7002 c l c u 0.01f pgnd pwm2 gnd boot2 +5v or +12v figure 1. HIP6602B test circuit HIP6602B
8 typical performance curves figure 2. power dissipation vs freq uency figure 3. 1nf loading profile figure 4. 3nf loading profile figure 5. power dissipation vs loading figure 6. power dissipation vs frequency, pvcc = 5v figure 7. power dissipation vs frequency, pvcc = 5v 1200 1000 800 600 400 200 0 0 500 1000 1500 frequency (khz) power (mw) pvcc = 12v vcc = 12v c u = c l = 2nf c u = c l = 1nf c u = c l c u = c l c u = c l = 3nf = 4nf = 5nf 1200 800 600 400 200 0 0 500 1000 2000 frequency (khz) power (mw) 1500 pvcc = vcc = 12v 1000 c u = c l = 1nf c l = 1nf, c u = 0nf c u = 1nf, c l = 0nf 1200 800 600 400 200 0 0 500 1000 frequency (khz) power (mw) 1500 pvcc = vcc = 12v 1000 c u = c l = 3nf c l = 3nf, c u = 0nf c u = 3nf, c l = 0nf 10khz 30khz 100khz 200khz 500khz 12 345 1200 1000 800 600 400 200 0 power (mw) gate capacitance (c u = c l ), (nf) pvcc = vcc = 12v pvcc = 5v, vcc = 12v c u = c l = 4nf c u = c l = 5nf c u = c l = 2nf c u = c l =1nf 800 700 500 600 300 100 0 0 500 1500 2000 frequency (khz) power (mw) 1000 200 400 c u = c l = 3nf 0 500 1000 1500 2000 frequency (khz) 350 300 250 200 150 100 50 0 power (mw) pvcc = 5v, vcc = 12v c l = 1nf, c u = 0nf c u = c l = 1nf c u = 1nf, c l = 0nf HIP6602B
9 figure 8. power dissipation vs loading, pvcc = 5v typical performance curves (continued) 30khz 100khz 200khz 500khz 1mhz 2mhz 1.5mhz pvcc = 5v, vcc = 12v 5 4 3 2 1 power (mw) 600 500 400 300 200 100 0 gate capacitance (c u = c l ), (nf) HIP6602B
10 HIP6602B quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l16.5x5 16 lead quad flat no-lead plastic package (compliant to jedec mo-220vhhb issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.28 0.33 0.40 5, 8 d 5.00 bsc - d1 4.75 bsc 9 d2 2.55 2.70 2.85 7, 8 e 5.00 bsc - e1 4.75 bsc 9 e2 2.55 2.70 2.85 7, 8 e 0.80 bsc - k0.25 - - - l 0.35 0.60 0.75 8 l1 - - 0.15 10 n162 nd 4 3 ne 4 4 3 p- -0.609 --129 rev. 2 10/02 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.
11 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com HIP6602B small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. interlead flash and protrusions shall not ex ceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m14.15 (jedec ms-012-ab issue c) 14 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3367 0.3444 8.55 8.75 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n14 147 0 o 8 o 0 o 8 o - rev. 0 12/93

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